Personal Profile

I am a dedicated team player with a friendly and outgoing personality, who welcomes the challenges involved in the microelectronics industry.

Through these years at Stmicroelectronics and Atmel I gained enough experience to be responsible for the P&R flow for several projects. Multi million hierarchical IC's using Synopsys (Astro), Magma or Cadence back-end tools, 0.18, 0.13, 0.90 (TSMC, ST, Atmel, Infineon, Futzitsu) technologies.

Currently I'm working for Atmel using Magma Blastfusion tools plus Infineon's 0.13, L90 and Futzitsu .90 technology.

As a member of a 2 people team I have involved in all aspects of design, having also good knowledge of timing issues and debugging.

Skills Summary

IC Layout Engineer including:

· Digital/Analogue Floorplaning

· Place & Route

· Physical Verification (DRC, LVS, Antenna, SI)

· Timing closure of design/Signoff

· Magma vs Primetime correlation

· Design automated P&R Flows

· Complete IC design from net list to GDSII

Tools Experience

Work Experience

Feb 2004 -

Company: Atmel (multimedia department)

Position: Sr Layout Engineer

· Netlist to GDSII -Design ownership.

· Floorplaning, IO, Timing closure, Power plan

· Tools: Cadence, Magma, StarXtract, Primetime, Calibre

· P&R flow development using Magma

· SI + OCV

· TCL, Unix scripts, mtcl

Products worked on:

AT76C522: Hi Performance Dual Band Residential Processor, Futzitsu 0.90,

Hierarchical design, 2 AVR microprocessors.

AT76C903: 802.11a/g with HMB VoiP Processor with Camera Controller

Infineon 0.90, 500K instances, multiVT

AT76C910: 802.11a/g Wireless VoiP, Infineon 0.13, 400K instances

AT76C521: Powerful Network Processor w/t ADSL2/2+, Infineon 0.13,

400K instances

AT76C515C: 802.11a/g MAC + Baseband, Infineon 0.13, 300K instances

AT76C902: 802.11a/g Wireless VoiP Processor, Atmel 0.18, 400K instances

AT76C520: Powerful Network Processor, Atmel 0.18, 200K instances

AT76C557: Btooth 1.2 Baseband with Audio Codec, Atmel 0.18, 200K instances

Nov 2002 - Dec 2003: Compulsory Military service completion

October 1999 - May 2002

Company: ST-Microelectronics, Graphics Product Division

Position: IC Physical Designer/Layout Engineer

Duties and Responsibilities:

· Develop and Automate P&R flow for 0.18 TSMC & 0.13 HCMOS9.

· Maintenance of HCMOS9 using new CAD tools as available

· Block level P&R ownership (netlist to routed designs)

· Reference Libraries checking/generation

· Physical verification at block/top level, DRC, LVS, Antenna

· Block level, timing closures including automated/manual ECO's

· Signal integrity / Antenna prevention in P&R block/top level flow

· Worked closely with central R&D Crolles (France) for the Development of ST's

AvantiKit

· Proposed changes to Avanti for CAD improvements (carried out)

· Training Digital Designers to work as layout engineers.

Products worked on:

Kyro Graphics Accelerator -13 Million transistors, TSMC 0.25um process

Kyro2 Graphics Accelerator - 15 Million transistors, TSMC 0.18um process

Kyro3 Prototype Graphics Accelerator 49 Million transistors, TSMC 0.18 process

Kyro3 Graphics Accelerator 45 Million transistors, HCMOS9 (TSMC 0.13) process

EDUCATION AND QUALIFICATIONS

1997-1999 University of Westminster, London, UK

MSc VLSI System Design

1994-1997 University of Westminster, London, UK

Beng Electronic Engineering

1992-1994 Technological Institute Kontoravdis, Athens, Greece

Diploma in Electronics Installations & Automation