Education

· 1997 - 2000Southampton University

· BEng degree in Electronic Engineering

· 1989 - 1996Bexley and Erith Technical High School for Boys, Bexley, Kent

A-Levels (June 1996)

· Mathematics A

· Physics A

· Design & Technology (Technology) B

· Geometrical & Mechanical Drawing C

GCSEs (June 1994)

· Technology, History A*

· Mathematics, French A

· Double Award Science BB

· English Language, English Literature, German, Music B

Work History

· July 2000 - April 2002

Excel Consultants Ltd. (High Wycombe)

ASIC Designer

Carrying out various ASIC and FPGA design and verification tasks.

· September 1996 - July 2000

BAE Systems (Avionics Division, Rochester)

previously known as;

Marconi Electronic Systems (Avionics Group)

and before that;

GEC-Marconi Avionics

Student Engineer

Within the ASIC Group - CPLD, FPGA and ASIC design and testing.

Year out placement before university and two summer vacation placements.

Total of about 80 weeks experience.

· 1997 - 1999 Bencraft Court (University Hall of Residence) Bar

Part time bar work.

Other Responsibilities

· April 1998 - June 1999 JCR committee member - Bencraft Court (University Hall)

· April 1998 - October 1998 Assistant Bar Treasurer - Bencraft Court

· October 1998 - June 1999 Bar Manager - Bencraft Court

The bar manager position was that of greatest responsibility. I had overall responsibility for all stock checking and ordering, staff rota, equipment maintenance and till cashing up. I trained several staff and supervisors, had to keep the staff happy in their work, and of course served customers. I certainly enhanced organisational, leadership, management and communication skills during that time.

Skills

· Full driving licence since November 1995

· IT skills

· Knowledge of C

· Knowledge of HTML

· Excellent general computer skills

· Familiar with Microsoft Word, Excel, Publisher, Outlook

· Familiar with using Windows, UNIX and LINUX operating systems

ASIC and FPGA design experience

I have about three and half years experience of various elements of ASIC and FPGA design and testing. I have experienced the whole design flow from small FPGAs up to a multi million gate ASIC.

· Design and verification related skills

· VHDL and Verilog

· Verisity's 'e' verification language

· Embedded processor and SoPC with Altera ARM-Excalibur

· ARM assembler for use with Altera ARM-Excalibur

· Altera ARM-Excalibur development board

· Design flow experience

· Design capture, compilation, simulation, verification

· Synthesis, scan insertion, static timing analysis

· ATPG vector generation and testing

· ASIC and FPGA tools familiarity

· Compilation and Simulation - Modelsim

· Verification - Verisity Specman

· ASIC Synthesis, Scan Insertion and Static Timing Analysis - Cadence Ambit Buildgates

· FPGA Synthesis - Exemplar Leonardo

· Good knowledge of Altera Quartus for APEX devices and ARM-Excalibur

· Altera ARM-Excalibur development board

· Other FPGA vendor's tools - Xilinx, Cypress, Quicklogic, Actel

· ATPG vector generation and testing - Synopsys Tetramax

· ASIC vendor experience - Atmel (including using their netlist and vector checking tool)

Interests

· Music Competent playing violin, clarinet and saxophone - not currently part of any groups

but still play for personal enjoyment and relaxation.

· Sport Have previously regularly played rugby and cricket at club level. Now play cricket

occasionally and enjoy badminton and tennis recreationally.